Correction bit 5 12

Connected to the box is a v power cable providing AC power at 50Hz. Above the computer is a light fitting with a flourescent tube, starter and transformer buzzing away at more than v and Hz.

Your friend sitting at the next computer is talking on a mobile phone. Its carrier is probably at Mhz or thereabouts. Another friend is wearing clothes made from some synthetic fabric, has on rubber soled sports shoes and has been scuffing them on the synthetic carpet that covers the lab floor. That friend just brushes past the cabling at the back of the computer causing a huge discharge of static electricity. All of the above cause electromagnetic interference that can introduce errors into the electrical signals that flow on the buses through the computer.

As most of our storage media are magnetic also, data stored on disks and tapes is also susceptible to corruption. Errors can be so huge that the computer crashes and needs to reboot. More often than not, errors are small and consist of one or two bits in a binary number having been inverted. Inverting a '0' gives a '1' and vice versa Such errors may only be small but can cause large damage in the wrong application.

In webpage design there are colours that are represented as 6 digit hexadecimal numbers. Imagine if we sent data to the video card to set a particular pixel to white.

The 32bit binary number for that colour is:. So, our computer screen has one pixel out of 50, that is orange instead of white. So what you ask? Imagine some accounting software is sending an account balance to the database for storage. Imagine if a data error crept in here! The figure being written to the database is now: Which is a hell of an accounting charge!!

This can be a serious problem! The remainder of this module is devoted to the discussion of techniques for detecting and later correcting errors in data. When information is stored in memory either in random access electronic memory or magnetic media we need some way of guarding against corruption.

There has been a great deal of work over the years in this area. It was pioneered by Hamming in The main idea is to add some redundant information to the data to allow for error detection, and maybe even correction.

If two words have a Hamming distance of d then they require d single bit errors in order to convert one into another.. Consider allocating n bits to a code word, of which m are for data and r bits are redundant. If we declare that is the only legal representation for the hexadecimal number 2C base16, then if turns up we know that it cannot be the value 2C base Given an algorithm for computing the check bits, it is possible to construct a complete list of all the legal code words.

The location of FEC blocks within transport overhead will be described in more detail below. According to the principles of the invention, forward error correction can be applied to the entire frame so that errors can be corrected in both transport overhead and payload , with some exceptions that will be noted below.

It should be noted that FIG. Other variations and modifications will be apparent to those skilled in the art and are contemplated by the teachings herein. Deciding on the appropriate number of FEC blocks for each row will depend on several considerations, including the type of forward error correction code being used, available overhead in the row, and the state of technology being used for device implementation, to name a few.

In any case, the complexity associated with parallel processing forward error correction algorithms is substantially reduced according to the principles of the invention as compared with the prior arrangements.

Using four 4 FEC blocks per row as an example, only four forward error correction processes must be carried out at a time because row-by-row processing allows for the reuse of the same forward error correction circuitry for each row. As shown, FEC block comprises four 4 bytes - of correction bits for a total of 32 correction bits. It should be noted that 32 correction bits is only one exemplary embodiment for a FEC block and more correction bits may be used depending on the type and strength of the forward error correcting code selected.

In addition to the correction bits which are used for correcting errors in the corresponding blocks of data within each row, error detection code can also be mapped along with the correction bits into the corresponding transport overhead of the rows. For example, error detection techniques such as bit interleaved parity BIP , cyclic redundancy checks CRC , and other well-known coding techniques for detecting multiple errors can be employed to ensure that forward error correction is only enabled when the number of errors in a row does not exceed the bit error correction capability of the forward error correction code being used.

For simplicity of explanation, 8-bit interleaved parity BIP- 8 will be used as an exemplary embodiment. It should be noted, however, that this particular embodiment is only meant to be illustrative and not limiting. As will be described in more detail below, BIP- 8 parity can be used for judiciously controlling when forward error correction is enabled and disabled. For example, if BIP- 8 parity detects multiple errors in a row that exceeds the capability of the forward error correction algorithm, i.

It should be noted that the above byte definitions illustrate just one example for mapping forward error correction into a STS- signal. Other modifications can be made consistent with the teachings herein. For example, the byte definitions may vary depending on the strength of the particular forward error correction algorithm selected. For the most efficient use of unused overhead to carry forward error correction bytes according to this mapping scheme, it is contemplated that the selected forward error correction algorithm should not use more than 24 overhead bytes per row although more unused overhead is available as will be described below.

Referring again to FIG. The specific placement of FEC bytes as shown in this embodiment provides one optimized solution for mapping forward error correction, however, this embodiment is only intended to be illustrative and not limiting as other alternative placements are possible. As shown in FIG. For completeness, the detailed placements of FEC bytes in these rows will also be described with reference to the equivalent rate SDH signal, i. In particular, FEC bytes corresponding to block A in rows 1 - 3 and 5 - 9 i.

Similarly, FEC bytes corresponding to block B in rows 1 - 3 and 5 - 9 i. FEC bytes corresponding to block C in rows 1 - 3 and 5 - 9 i. Finally, FEC bytes corresponding to block D in rows 1 - 3 and 5 - 9 i. In operation, FEC start byte can be beneficially used if an application requires corrections to be enabled or disabled in-service without causing hits on traffic.

Because row 4 does not include unused overhead as in rows 1 - 3 and 5 - 9 , an alternative mapping scheme is contemplated using the H 1 bytes in row 4. For purposes of this mapping scheme, it is contemplated that the FEC bytes can be carried in S 0 bit locations of H 1 bytes in row 4. More specifically, S 0 bits in succeeding H 1 bytes in row 4 line overhead must be used to carry the 20 FEC bytes for row 4 i.

It should be noted that selection of the H 1 byte and selection of the S 0 bit within the H 1 byte to carry the FEC bytes for row 4 represents only one illustrative embodiment. For example, other overhead bytes could be used. Moreover, the S 1 bit in the H 1 byte could also be used in a similar manner as that described for the S 0 bit. In yet another alternative embodiment, both the S 0 and S 1 bits could be used together so that only half the number of succeeding H 1 byte frames i.

More specifically, FEC bytes corresponding to block A in row 4 i. It should be noted that, for SDH applications, the SS bit mismatch may need to be disabled for STM- 64 interfaces in accordance with applicable standards. Although the S 0 overhead bits in row 4 are overwritten with FEC bytes, these overwritten bytes can be preserved using rearrangements as will be described below.

Rearrangements may also be used in anticipatory fashion to accommodate future changes to standards which may result in a presently undefined overhead byte becoming defined for a particular use. One example is the Z 0 growth byte that will be described below.

Rearrangement is a relatively straightforward process in which the contents of overwritten byte and bit locations are copied and mapped to other time slots, e. This rearrangement technique can therefore preserve the contents of overwritten overhead e. If these Z 0 growth bytes are later defined, then it may become desirable to preserve the contents of incoming Z 0 bytes. This can be accomplished through rearrangements whereby the contents of the overwritten Z 0 bytes are copied to unused overhead in another row, e.

After FEC decoding is completed, the contents of the Z 0 bytes can be moved back to the original time slots in row 1 in the reverse manner. Similarly, mapping FEC bytes for row 4 overwrite the S 0 pointer bits as previously described.

If it becomes necessary to preserve the contents of incoming S 0 bits, the contents can be moved to unused overhead in another row, e.

After FEC decoding is completed, the contents can be copied back into the S 0 bit locations in row 4. The above examples are only illustrative of two possible rearrangement scenarios for preserving the contents of overwritten bits and bytes. In operation, as shown in FIG. After section overhead transmit byte processing block , the Z 0 bytes are rearranged block in the manner previously described, e. Similarly, the S 0 bits from the H 1 bytes in row 4 are preserved block by copying and inserting the contents of these bits into row 5.

After the S 0 bits are rearranged, B 2 byte compensation is carried out block due to the S 0 rearrangements. B 2 byte compensation will be described in more detail below. FEC correction bits are then calculated and inserted within the frame as shown in block In particular, the 16 FEC correction bytes i. Because row 1 overhead is not scrambled like in the other rows, the FEC blocks for row 1 , e. The FEC start byte is then inserted as shown in block If a regenerator bypass mode is applicable, represented by block , then the FEC overhead bytes, FEC start byte, and rearranged Z 0 bytes and S 0 bits would pass through unaltered.

For the embodiment shown and described herein, it should be noted that B 2 byte compensation e. FEC encoder block can be implemented using well-known techniques performed by hardware, software, application specific integrated circuits ASICs , or a combination thereof. After descrambling, the FEC start byte is located block and, depending on the value of the start byte, forward error correction will either be enabled to allow corrections or disabled as shown.

FEC blocks for row 1 , i. As previously described, FEC BIP- 8 parity can be used to detect multiple errors and to appropriately enable or disable forward error correction depending on whether the number of errors detected is within the correction capability of the selected forward error correction algorithm.

After data is stored block , FEC correction bits are then calculated block to determine the location of any errors. Correction of bit errors can then take place as shown in block assuming that error correction has not been disabled. The Z 0 bytes and S 0 bits are then rearranged as shown in blocks and , respectively, by copying the contents back into their respective rows.

For example, the B 2 byte requires compensation for removing the FEC correction bits from row 4. FEC decoder block can be implemented using well-known techniques performed by hardware, software, application specific integrated circuits ASICs , or a combination thereof.

As previously described, the B 1 and B 2 bytes in this embodiment are kept intact for transmission. As such, the B 2 byte must be compensated to account for the rearrangements and insertion of the FEC bytes. For example, B 2 byte compensation due to the S 0 rearrangements block is required because moving the contents of the S 0 bits in row 4 to row 5 results in overwriting the contents of the applicable row 5 bit locations, e. Consequently, B 2 byte compensation is required to maintain accurate parity within row 5 , e.

Similarly, B 2 byte compensation is required to maintain accurate parity within row 4 after the FEC bytes are inserted block It should also be noted that, in certain implementations, shifting contents between time slots may not necessarily impact B 2 parity depending on which time slots are selected for carrying out the shifting.

As previously indicated, the embodiments shown and described herein are only meant to be illustrative and not limiting. For example, in the above-described embodiments, 5 FEC bytes 4 bytes of correction bits and 1 byte of BIP- 8 parity are mapped for each of the 4 blocks in a given row so that a total of 20 FEC bytes are mapped into each row.

However, it should be noted that the mapping scheme according to the principles of the invention can be used to map up to 48 FEC bytes per row. Accordingly, the number of blocks per row and the number of FEC bytes per block may vary depending on the particular forward error correction code selected for the application and other factors previously described. One of many examples of a suitable forward error correction algorithm that can be mapped to a STS- signal according to the principles of the invention is a double bit error correction BCH code i.

Some of the performance advantages associated with using a BCH- 2 code in conjunction with the mapping scheme of the invention are illustrated in FIGS. As shown, curve represents an uncorrected bit error rate, curve represents a bit error rate corrected using a single-error correcting Hamming code according to the principles of the invention, and curve represents a bit error rate corrected using a double bit error correction BCH- 2 code according to the principles of the invention.

Performance advantages will of course vary depending on the type and strength of the forward error correction code selected. Consequently, the performance advantages shown in FIGS. According to another aspect of the invention, a burst error correction capability can be obtained by bit interleaving the forward error correction blocks as shown in FIG.

In particular, bit interleaving improves the burst error correction capability because multiple contiguous bit errors will be mapped to different forward error correction blocks and each forward error correction block can correct multiple errors.

As previously indicated, forward error correction can be applied to an entire SONET frame so that errors can be corrected in both the transport overhead and payload, with some exceptions. For example, the FEC start byte may change values during transmission as a result of a facility defect, for example. As such, applying FEC to the start byte may result in a false correction. Section overhead also should not be covered by FEC blocks if a line terminating element to line terminating element capability is desired.

For example, section overhead may be overwritten at regenerators e. Consequently, if a section overhead row was covered by a FEC block, then regenerators would always need to provide FEC decoding and encoding, which would add additional delay. Section overhead can therefore be handled as follows.

In one illustrative embodiment, section overhead bytes for rows 1 - 3 are assumed to be zero for purposes of FEC encoding and decoding. That is, a zero is assigned for each FEC correction bit corresponding to the section overhead bytes.

Although errors in the section overhead will not be corrected using this approach, additional delay is avoided which would otherwise occur as a result of FEC decoding and encoding at regenerators.

It may be desirable in some applications that FEC blocks do not cover the B 2 and Z 0 bytes and S 0 bits because of the rearrangements. If this is the case, then these bytes and bits can be handled as follows. The B 2 bytes are assumed to be zero for both FEC encoding and decoding. This implementation serves to eliminate some feedback paths from B 2 after it is compensated for the FEC calculation function.

The Z 0 bytes row 1 and S 0 bits row 4 are rearranged to preserve the contents as previously described. Therefore, in the receive direction, the preserved values, which are not corrected, overwrite the Z 0 and S 0 contents. Similar exceptions may be necessary for applying forward error correction scheme to other types of signals depending on operational or signal structure limitations specific to the particular signal. Consequently, techniques that are similar to those described above may be employed in modifying the mapping approach and application of forward error correction for a given signal structure depending on the particular exceptions.

It should also be noted that the techniques described above are only meant to be illustrative and not limiting. For example, an all-ones approach may be used instead of an all-zeros approach. According to another aspect of the invention, forward error correction can also be enabled and disabled based on different criteria or events.

Among other advantages, judicious control of forward error correction according to the principles of the invention can therefore prevent miscorrections, e. Minimizing delay in a forward error correction scheme is a significant consideration for many SONET applications. For example, virtual concatenation, which is a way to handle many STS- 1 signals as a group without carrying them as a contiguous bundle, requires minimal differential delay among the STS- 1 signals.

Protection switching is another application that is very sensitive to delay. For example, switching decisions in hardware-based protection switching and hitless protection switching schemes must occur with minimal delay. Consequently, these bytes must be sent between network elements as fast as possible. In view of these and other delay-sensitive applications, the mapping scheme according to the principles of the invention can be beneficially applied to achieve extremely low delays while improving the overall bit error rate performance of a system.