4 bit ripple counter using jk flip flop truth table

Each output represents one bit of the output word, which, in 74 series counter ICs is usually 4 bits long, and the size of the output word depends on the number of flip-flops that make up the counter. The output lines of a 4-bit counter represent the values 2 0 , 2 1 , 2 2 and 2 3 , or 1,2,4 and 8 respectively. They are normally shown in schematic diagrams in reverse order, with the least significant bit at the left, this is to enable the schematic diagram to show the circuit following the convention that signals flow from left to right, therefore in this case the CK input is at the left.

The rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half the frequency of the CK pulses applied to its input.

The Q outputs then represent a four-bit binary count with Q 0 to Q 3 representing 2 0 1 to 2 3 8 respectively. Assuming that the four Q outputs are initially at , the rising edge of the first CK pulse applied will cause the output Q 0 to go to logic 1, and the next CK pulse will make Q 0 output return to logic 0, and at the same time Q 0 will go from 0 to 1.

The next third CK pulse will cause Q 0 to go to logic 1 again, so both Q 0 and Q 1 will now be high, making the 4-bit output 2 3 10 remembering that Q 0 is the least significant bit. The fourth CK pulse will make both Q 0 and Q 1 return to 0 and as Q 1 will go high at this time, this will toggle FF2, making Q 2 high and indicating 2 4 10 at the outputs. Reading the output word from right to left, the Q outputs therefore continue to represent a binary number equalling the number of input pulses received at the CK input of FF0.

As this is a four-stage counter the flip-flops will continue to toggle in sequence and the four Q outputs will output a sequence of binary values from 2 to 2 0 to 15 10 before the output returns to 2 and begins to count up again as illustrated by the waveforms in Fig 5.

To convert the up counter in Fig. By taking both the output lines and the CK pulse for the next flip-flop in sequence from the Q output as shown in Fig. Although both up and down counters can be built, using the asynchronous method for propagating the clock, they are not widely used as counters as they become unreliable at high clock speeds, or when a large number of flip-flops are connected together to give larger counts, due to the clock ripple effect.

The effect of clock ripple in asynchronous counters is illustrated in Fig. As the Q 0 to Q 3 outputs each change at different times, a number of different output states occur as any particular clock pulse causes a new value to appear at the outputs.

At CK pulse 8 for example, the outputs Q 0 to Q 3 should change from 2 7 10 to 2 8 10 , however what really happens reading the vertical columns of 1s and 0s in Fig. At CK pulses other that pulse 8 of course, different sequences will occur, therefore there will be periods, as a change of value ripples through the chain of flip-flops, when unexpected values appear at the Q outputs for a very short time.

However this can cause problems when a particular binary value is to be selected, as in the case of a decade counter, which must count from 2 to 2 9 10 and then reset to 2 on a count of 2 10 These short-lived logic values will also cause a series of very short spikes on the Q outputs, as the propagation delay of a single flip-flop is only about to ns.

Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a simple and effective frequency divider, where a high frequency oscillator provides the input and each flip-flop in the chain divides the frequency by two. The synchronous counter provides a more reliable circuit for counting purposes, and for high-speed operation, as the clock pulses in this circuit are fed to every flip-flop in the chain at exactly the same time.

Synchronous counters use JK flip-flops, as the programmable J and K inputs allow the toggling of individual flip-flops to be enabled or disabled at various stages of the count. Synchronous counters therefore eliminate the clock ripple problem, as the operation of the circuit is synchronised to the CK pulses, rather than flip-flop outputs.

Notice that the CK input is applied to all the flip-flops in parallel. Therefore, as all the flip-flops receive a clock pulse at the same instant, some method must be used to prevent all the flip-flops changing state at the same time. This of course would result in the counter outputs simply toggling from all ones to all zeros, and back again with each clock pulse. However, with JK flip-flops, when both J and K inputs are logic 1 the output toggles on each CK pulse, but when J and K are both at logic 0 no change takes place.

The binary output is taken from the Q outputs of the flip-flops. Note that on FF0 the J and K inputs are permanently wired to logic 1, so Q 0 will change state toggle on each clock pulse. In adding a third flip flop to the counter however, direct connection from J and K to the previous Q 1 output would not give the correct count.

Because Q 1 is high at a count of 2 10 this would mean that FF2 would toggle on clock pulse three, as J2 and K2 would be high. Therefore clock pulse 3 would give a binary count of 2 or 7 10 instead of 4 To prevent this problem an AND gate is used, as shown in Fig. Only when the outputs are in this state will the next clock pulse toggle Q 2 to logic 1.

The outputs Q 0 and Q 1 will of course return to logic 0 on this pulse, so giving a count of 2 or 4 10 with Q 0 being the least significant bit. Q 3 therefore will not toggle to its high state until the eighth clock pulse, and will remain high until the sixteenth clock pulse. After this pulse, all the Q outputs will return to zero. Note that for this basic form of the synchronous counter to work, the PR and CLR inputs must also be all at logic 1, their inactive state as shown in Fig.

Converting the synchronous up counter to count down is simply a matter of reversing the count. If all of the ones and zeros in the 0 to 15 10 sequence shown in Table 5. As every Q output on the JK flip-flops has its complement on Q , all that is needed to convert the up counter in Fig. Each group of gates between successive flip-flops is in fact a modified data select circuit described in Combinational Logic Module 4.

This is necessary to provide the correct logic state for the next data selector. If the control input is at logic 1 then the CK pulse to the next flip-flop is fed from the Q output, making the counter an UP counter, but if the control input is 0 then CK pulses are fed from Q and the counter is a DOWN counter.

When Q 1 and Q 3 are both at logic 1, the output terminal of the limit detection NAND gate LD1 will become logic 0 and reset all the flip-flop outputs to logic 0. Because the first time Q 1 and Q 3 are both at logic 1 during a 0 to 15 10 count is at a count of ten 2 , this will cause the counter to count from 0 to 9 10 and then reset to 0, omitting 10 10 to 15 The circuit is therefore a BCD counter, an extremely useful device for driving numeric displays via a BCD to 7-segment decoder etc.

However by re-designing the gating system to produce logic 0 at the CLR inputs for a different maximum value, any count other than 0 to 15 can be achieved. Because of this control, the addition of a common clock will synchronize data transfer and all flip-flops will change state simultaneously.

The important feature of a synchronous counter is that the transitions of the individual flip-flops are synchronized to a master clock signal. J-K flip-flops are normally used in the synchronous counters due to the enabling controlling feature of the J and K inputs.

There are two basic schemes for generating the J and K inputs. One of them is illustrated in the four-bit binary counter shown in Fig.

Notice that the information to the J-K inputs is formed in a parallel fashion. The counter is accordingly termed as synchronous parallel counter. In the parallel scheme the number of inputs to each AND gate increases linearly with the number of stages.

For this added expense one gets the fastest possible synchronous counting circuit. If the J-K input information is formed from the output of the AND gate in the previous stage, one has a synchronous serial counter. Although the serial scheme is slower than the parallel scheme, the number of inputs to the AND gate per stage is constant in the serial case two inputs per stage. Connect the count-up ripple counter shown in Fig.

Set data switch SW1 from logic 0 to logic 1 clear all flip-flops. Now connect CLK to a pulse generator in your pencil box J-K flip-flops in 74LS76 are negative edge triggered and start counting by pushing the pulser button. Continue the process and record the output of each transition in a truth table. Does it count correctly? We can convert the count-up ripple counter to a count-down ripple counter by connecting the clock of the flip-flops to Q instead of Q the LEDs are still connected to Q.

Make the modification and try out the circuit. Connect the 4-bit synchronous parallel counter as shown in Fig. Repeat the same procedures in the ripple counter experiment.