10 bit carry ripple adder subtractor

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This paper first presents a study 10 bit carry ripple adder subtractor the classical BCD adders from which a carry-chain type adder is redesigned to fit within the Xilinx FPGA's platforms. Some new concepts are presented to compute the P and G functions for carry-chain optimization purposes. Several alternative designs are presented.

All designs are presented with the corresponding time performance and area consumption figures. Results have been compared to straight implementations of a decimal ripple-carry adder and an FPGA 2's complement binary adder-subtractor 10 bit carry ripple adder subtractor the dedicated carry logic, both carried out on the same platform.

Better time delays have been registered for decimal numbers within the same range of operands. In a number of computer arithmetic applications, decimal systems are preferred to the binary ones. Decimal arithmetic plays a key role in data processing environments such as commercial, financial, and Internet-based applications [ 1 — 3 ]. Performances required by applications with intensive decimal arithmetic are not met by most of the conventional software-based decimal arithmetic libraries [ 1 ].

Hardware implementation embedded in recently commercialized general purpose processors [ 34 ] is gaining importance. Furthermore, IEEE has recently published a new standard [ 5 ] that supports the floating point representation for decimal numbers. Although other coding systems may be of interest, BCD seems to be the best choice until now.

Issues of hardware realization of decimal arithmetic units appear to be 10 bit carry ripple adder subtractor open: This paper resumes some 10 bit carry ripple adder subtractor concepts about carry-chain type algorithms for adding BCD numbers.

Two key ideas have been introduced: Signed numbers addition is used as a primitive operation for computing most arithmetic functions, so that it deserves particular attention.

It is well known that in classical algorithms the execution time of any program or circuit is proportional to the number N of digits of the operands. In order to minimize the computation time, several ideas have been proposed in the literature [ 89 ].

Most of them consist in modifying the classical algorithm in such a way as to minimize the computation time of each carry; the time 10 bit carry ripple adder subtractor may still be proportional to Nbut the proportionality constant may be reduced. Moreover, it has to be pointed out that, within the same range, decimal addition involves shorter carry propagation process than for the straight binary code.

It will be shown in the practical implementations that adding BCD digits can not only save coding interfaces but moreover provides time delay reductions. Hardware consumption for BCD will be greater, if coding and decoding processes are not considered; as of today, the dramatic decreasing of hardware cost stimulates work on time saving.

In this paper, decimal carry-chain and ripple-carry adders have been implemented on Virtex-4 Xilinx FPGA platforms, for a number of operand sizes; comparative performances are presented for binary and BCD digit operands. Additionally, three implementations of adders-subtractors have been implemented on FPGA Xilinx Virtex-5 platforms for a number of operand sizes; comparative performances are presented for binary and BCD digit operands, respectively.

Consider the base- representations of two - digit numbers:. Algorithm 1 pencil and paper computes the -digit representation of the sum where is an initial carry equal to 0 or 1. Classic addition ripple carry: As is a function of the execution time of Algorithm 1 is proportional to Figure 1. In order to reduce the execution time of each iteration step, Algorithm 1 can be modified as shown in Section 3. First define two binary functions of two -valued variables, namely, the propagate and generate functions:.

The next carry can be calculated as follows:. Carry-chain addition — computation of the generation and propagation conditions: Comments 1 Instruction sentence 3 is equivalent to the following Boolean equation: Furthermore, if the preceding relation is used, then the definition of the generate function can be modified: If the preceding relation is used, then the definition of the propagate function can be modified:.

The structure of an -digit adder with separate carry calculation is shown in Figure 2. It is based on Algorithm 2. The Generate-Propagate cell calculates the Generate and Propagate functions 2. As regards the computation timethe critical path is shaded in Figure 2. It has been assumed that. Another interesting time is the delay from to assuming that all propagate and generate functions have already been calculated:.

Equation 4 can be implemented by a 2-to-1 binary multiplexer Figure 3 a while 6 by a 2-gate circuit Figure 3 b. In the first case, the per-digit-delay of a carry-chain adder is equal to the delay of a 2-to-1 binary multiplexer, whatever the base B is. If and the carry-chain cell of Figure 3 a is used, then 10 bit carry ripple adder subtractor can be chosen equal to, for example.

The corresponding cell for a -bit binary adder is shown in Figure 4. 10 bit carry ripple adder subtractor one-to-one function R xassociating a natural number to x, is defined as follows. Actually the only case that cannot be represented with n digits is whensothat is to say The computation of the representation of is based on the following property.

A straightforward inversion algorithm then consists in representing x with digits, complementing every digit to 9, then adding 1. Observe that sign extension is obtained by adding a digit 0 to the left of a positive number or 9 for a negative number, respectively. Observe that the critical path involves the carry propagation through 7 binary adders plus a 4-bit Boolean circuit checking if the sum 10 bit carry ripple adder subtractor greater than 9 or not.

A straightforward way to synthesize P and G is shown at Figure 6. Nevertheless, functions P and G may be directly computed from inputs. The following formulas 18 are Boolean expressions of conditions 17.

The BCD carry-chain adder i th cell is shown at Figure 7. Otherwise, the add- 6 correction applies. With more hardware consumption, but saving time delays, formulas 18 may be used. In what follows the area is expressed in LUT s. VHDL models are available at [ 11 ]. The classic implementation of the ripple carry adder cell in FPGA implies a 4-bit adder, a 4-LUT to detect the carry condition, and a final 3-bit adder.

The delay and area consumption of an N -digit ripple carry adder are. In order to make the best use of the resources, the design has been achieved using relative location techniques RLOC [ 12 ] with low-level component instantiations. The adding stages are implemented as shown at Figures 8 a and 8 b while the carry-chain structure with the 10 bit carry ripple adder subtractor functions has been implemented as shown at Figure 9 where G is computed according to Figure 6while P is computed as.

Figure 9 emphasizes that G depends on while P is computed from and G. The time delay corresponding to the 4-bit adder stage Figure 8 a and the output adder stage Figure 8 b is given as. Both adder stages of Figures 8 a and 8 b need the same hardware requirement; computed in slices, the area consumption is given as.

The complexity figures of the carry-chain circuit for a 4-digit unit, as shown at Figure 9are given as. The overall circuit is represented in Figure The overall time delay is computed from formulas 2122 and From 23 and 25the area requirement may be computed as. Functions P and G may be directly computed from x i and y i inputs using the Boolean expression The corresponding time and area of a carry-chain cell using this architecture is.

The complete cell includes a 4-bit adder and a conditional 3-bit output adder adding 6 whenever necessary similar to Figure 5. The overall time delay and area consumption using this carry-computation cell is:. Another alternative is 10 bit carry ripple adder subtractor on the use of dedicated multiplexers. Xilinx Spartan 3, Virtex-2, and Virtex-4 devices have Look-Up Table multiplexers muxf5, muxf6, muxf7, muxf8 in order to construct functions of 5, 6, 7, and 8 variables without using the general purpose routing fabric.

The complete cell also includes 4-bit adder and a conditional 3-bit adder. In a first version, Ad -I, the adding stage and correction stage are implemented as shown at Figures 8 a and 8 brespectively, while the carry-chain structure with the G-P functions is computed according to Figure 6. In a second version, Ad- II, the carry-chain is speeded up thanks to a direct computation of the G-Pnamely, using inputs instead of the intermediate sum bits. For this purpose one could use formulas 18 ; nevertheless, in order to minimize time and hardware consumption the implementation of and is revisited as follows.

Remembering that whenever the arithmetic sum one defines a 6-input function set to be 1 whenever the arithmetic sum of the first 3 bits of and is 4. Then may be computed as. On the other hand, is defined as a 6-input function set to be 1 whenever the arithmetic sum of the first 3 bits of and is 5 or more. So, remembering that whenever the arithmetic sum may be computed as.

To compute similar algorithm as in Section 7. The AS -I circuit is similar to the Ad -I Figures 8 and 13 using, instead of inputthe input as produced by the circuit of Figure As far as addition is concerned, the P and G functions may be implemented according to formulas 36 and For this reason, assuming that the operation at hand isone defines on one hand ppa i and gga i according to Section 7.

On the other hand, pps i and ggs i are defined according to the same Section 7. As are expressed from the 38both pps i and ggs i may be computed directly 10 bit carry ripple adder subtractor x k i and y k i as shown in Figure Nevertheless, for subtraction, the computation of is carried out at the 10 bit carry ripple adder subtractor LUT level. So formulas 36 and 37 are then expressed as. Performances of different N -digit BCD adders have been compared to those of an M -bit binary carry chain adder implemented by XST [ 13 ] using Xilinx fast carry logic covering the same range, that is, as.

Formulas 263034and 42 show that, asymptotically, should be somewhat inferior to. Nevertheless, as shown by the experimental results, the additive values appearing in 2630and 34 are 10 bit carry ripple adder subtractor negligible for reasonable values of N ; so the saving in time will mainly appear for applications where BCD-to-binary coding and decoding operations play a significant role in the overall delay.

Post place-and-route time delays and area consumptions are quoted in Tables 1 and 2respectively, where N stands for the number of BCD digits while M stands for the number of bits required to cover the decimal N -digit range. The results presented in 10 bit carry ripple adder subtractor table are as follows:. Figure 18 shows the delays for the compared adders.

An adder is a digital circuit that performs addition of numbers. In many computers and other kinds of processors adders are used in the arithmetic logic units or ALU.

They are also utilized in other parts of the processor, where they are used to calculate addressestable indices, increment and decrement operatorsand similar operations. Although adders can be constructed for many number representationssuch as binary-coded decimal or excess-3the most common adders operate on 10 bit carry ripple adder subtractor numbers.

In cases where two's complement or ones' complement is being used to represent negative numbersit is trivial to modify an adder into an adder—subtractor. Other signed number representations require more logic around the basic adder.

The half adder adds two single binary digits A and B. It has two outputs, sum S and carry C. The carry signal represents an overflow into the next digit of a multi-digit addition. With the addition of an OR gate to combine their carry outputs, two half adders can be combined to make a full adder. The input variables of a half adder are called the augend and addend bits. The output variables are the sum and carry. The truth table for the half adder is:. A full adder adds binary numbers and accounts for values carried in as well as out.

A one-bit full-adder adds three one-bit numbers, often written as A 10 bit carry ripple adder subtractor, Band C in ; A and B are the operands, and C in is a bit carried in from the previous less-significant stage.

The circuit produces a two-bit output. A full adder can be implemented in many different ways such as with a custom transistor -level circuit or composed of other gates. In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic.

Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip. Assumed that an XOR-gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to. It is possible 10 bit carry ripple adder subtractor create a logical circuit using multiple full adders to add N -bit numbers.

Each full adder inputs a C inwhich is the C out of the previous adder. This kind of adder is called a ripple-carry 10 bit carry ripple adder subtractor RCAsince each carry bit "ripples" to the next full adder. The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate delay can easily be calculated by inspection of the full adder circuit.

Each full adder requires three levels of logic. The carry-in must travel through n XOR-gates in adders and n carry-generator blocks to have an effect on the carry-out. To reduce the computation time, engineers devised faster ways to add two binary numbers by using carry-lookahead adders CLA. They work by creating two signals P and G for each bit position, based on whether a carry is propagated through from a less significant bit position at least one input is a 1generated in that bit position both inputs are 1or killed in that bit position both inputs are 0.

In most cases, P is simply the sum output of a half adder and G is the carry output of the same adder. After P and G are generated, the carries for every bit position are created. Some other multi-bit adder architectures break the adder into blocks. It is possible to vary the length of these blocks based on the propagation delay of the circuits to optimize computation time.

These block based adders include the carry-skip or carry-bypass adder which will determine P and G values for each block rather than each bit, and the carry select adder which pre-generates the sum and carry values for either possible carry input 0 or 1 to the 10 bit carry ripple adder subtractor, using multiplexers to select the appropriate result when the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. Other adder designs include the carry-select adderconditional sum addercarry-skip adderand carry-complete adder. If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal.

After all stages of addition, however, a conventional adder such as the ripple-carry or the lookahead must be used to combine the final sum and carry results. A full adder can be 10 bit carry ripple adder subtractor as a 3: The carry-out represents bit one of the result, while the sum represents bit zero. Likewise, a half adder can be used as a 2: Such compressors can be 10 bit carry ripple adder subtractor to speed up the summation of three or more addends.

If the addends are exactly three, the layout is known as the carry-save adder. If the addends are four or more, more than one layer of compressors is necessary, and there are various possible design for the circuit: This kind of circuit is most notably used in multipliers, which is why these circuits are also known as Dadda and Wallace multipliers.

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